Master clock frequencies and jitter performance
Sending the clock signal directly to the flip-flop, and not through the multiplexer, is a good idea, for sure. In my experience, a VHC is very good logic series, but it is of course the best to use none.
I am not that prone to using programmable clocks, for me this reads a PLL. I understand that they significantly improved recently, but I still like to keep things simple.
BTW, there are also the other ways to send the clock directly, and still have both necessary frequencies, by for instance using clocks' enable pins, so only one is active at the time. Theirs enable and disable times might be critical in this case, though.
As for the 16-bit frame and LE: no, I did not try this. But if we assume that tFBRL and tRBFL (referring to the datasheet) can be indeed 0 ns, then this might work. Not sure about the reliability of such a clocking timing, but I will try it once. It will not be easy to source 5.6448 MHz clocks, but this way we can make it up to 384 kHz compatible with 11.2896/12.288 MHz clocks.
Quote from Bartek on 26/03/2019, 18:41I see, in this context measuring the latch is less meaningful. But probably we can also deduce that the higher the clock noise the higher the jitter of the latch?
I guess the spectrum of the BCK in some way also influence the analogue output. As I learned already its _not_ that the digital inputs have nothing to the analog output and it is not only the jitter thing, in such complicated mixed signal devices as DACs..
Of course, the jitter (in time) and phase noise (in the frequency domain) are related.
The only thing we must have on mind here is that this relation also depends on the observed clock signal frequency. Roughly speaking, with given jitter, a phase noise increases with frequency, so by doubling the frequency, the noise is 6 dB higher.
Clock phase noise will be visible at the analog output of the DAC, and similar equations apply.
The year later, there is an update on this.
Actually for a couple of months now, the S4 DAC uses a better master clocks series. They are better both per manufacturers’ claims and my own measurements.
Also, these new clocks 22.5792 / 24.576 MHz performance is way closer to the performance of the previous 11.2896 / 12.288 MHz clocks. Subjectively, I can not say which is generally better, but in many ways I really prefer these new 22.5792 / 24.576 MHz ones.
Consequently, I settled on regularly using 22.5792 / 24.576 MHz frequencies in the S4, enabling the USB stage up to 384 kHz compatibility as a standard instead of an optional feature.
I will post the graphs later.
So, here it is. A 1.411 MHz bit clock with a new 22.5792 MHz master clock.
Some people asked me which ones these clocks were/are. No, it is not a secret, previously I used Kyocera, and these later clocks are Crystek.
Some of you who have the AYA 4 might have also noticed Kyocera clocks, and both AYA 4 series were using these. The second AYA 4 series (2019) was however different for using somewhat lower supply voltage for these clocks and re-clocker. I did that mostly to improve on the flip-flops performance, and there was no problem for Kyocera clocks to work this way, either.
At one point, I started to think about doing the same with S4 and Crystek. The "problem" here was that the Crystek clocks' officially claimed operating voltage was 3.3 VDC +/-10% – obviously, the datasheet did not encourage going below 3.3 V. Still, they do work at lower voltages, and apparently the low frequency jitter got better this way. I also contacted the manufacturer to check if they have any data in this regard, and they replied promptly, by sending the graph, which confirmed my findings and guesses. According to it, with 2.5 V supply voltage, the close-in jitter at 10 Hz is about 5 dBc/Hz better than with 3.3 V supply. Above 1 kHz, the noise floor gets 5-10 dB higher, however at -135 dBc/Hz or less (-160 dBc/Hz at 1 MHz), you might find it very low anyhow.
So, here is how the S4 works with USB Crystek master clocks supplied by 2.85 V. If you look more closely, you will notice the skirt a little tiny bit more narrow than at the graph above.
