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Master clock frequencies and jitter performance


Sending the clock signal directly to the flip-flop, and not through the multiplexer, is a good idea, for sure. In my experience, a VHC is very good logic series, but it is of course the best to use none.

I am not that prone to using programmable clocks, for me this reads a PLL. I understand that they significantly improved recently, but I still like to keep things simple.

BTW, there are also the other ways to send the clock directly, and still have both necessary frequencies, by for instance using clocks' enable pins, so only one is active at the time. Theirs enable and disable times might be critical in this case, though.

As for the 16-bit frame and LE: no, I did not try this. But if we assume that tFBRL and tRBFL (referring to the datasheet) can be indeed 0 ns, then this might work. Not sure about the reliability of such a clocking timing, but I will try it once. It will not be easy to source 5.6448 MHz clocks, but this way we can make it up to 384 kHz compatible with 11.2896/12.288 MHz clocks.

Quote from Bartek on 26/03/2019, 18:41

I see, in this context measuring the latch is less meaningful. But probably we can also deduce that the higher the clock noise the higher the jitter of the latch?

I guess the spectrum of the BCK in some way also influence the analogue output. As I learned already its _not_ that the digital inputs have nothing to the analog output and it is not only the jitter thing, in such complicated mixed signal devices as DACs..


Of course, the jitter (in time) and phase noise (in the frequency domain) are related.

The only thing we must have on mind here is that this relation also depends on the observed clock signal frequency. Roughly speaking, with given jitter, a phase noise increases with frequency, so by doubling the frequency, the noise is 6 dB higher.

Clock phase noise will be visible at the analog output of the DAC, and similar equations apply.