USB board Mk3 and AYA II revisited (proposal)

It looks like the USB interface and AYA II still draw your attention, and although none of them will be regularly available, they both can be released again as limited edition. Also, the idea with both designs is to move a bit, and make some progress. However we would need to know the actual interest first.  

So, here is the “survey”. It will remain open for the next two weeks or so.

 

USB INTERFACE BOARD Mk3 (8 CHANNEL)

 

USB interface would be mostly the same as previous Mk2 version, but this time with 8 channels I2S, or 4 channels if it outputs TDA1541A simultaneous data (or TDA1540, or PCM1704) protocol. It can be of course still used as stereo device, or quadraphonic, or typical 5.1 surround – it is all only about channel mapping. And there might be actually more of those who would use it for digital PC crossover in stereo system, than for classic multichannel playback.

Estimated price for completed module is 160-170 EUR. Timeframe: January – February 2018.

27 January 2018 EDIT: The form is now closed.

 

 

AYA II (2018) with ASYNC USB INPUT

 

AYA II might be redesigned, to include asynchronous USB Audio Class 2.0 front end. The S/PDIF input stage would be omitted, and the other input would be TDA1541A direct (sim. data or I2S), with U.FL connectors.

Estimated price is 600-650 EUR for kit which includes completed board and dedicated transformer, and 800 EUR for fully assembled device. Timeframe: the first half of 2018.

27 January 2018 EDIT: The form is now closed.

 

 

Related topics:

Plans for 2018

AYA 4: 2018 AYA release, featuring 192/384 kHz async USB

3 Replies

  1. 28-12-2017

    And here is some more information. Firstly, how does multichannel I2S look like?

    Putting aside master clock (MCK), which is usually required for oversampling filters and delta/sigma, but not for non-o/s DACs operation, a standard I2S has three signals: word select (WS) a.k.a. left-right clock (LRCK), then bit clock (BCK), and DATA.* In a nutshell, WS (LRCK) tells when binary word starts (by going low for left channel, and then going high for right channel). BCK tells when actual data (ones and zeroes) arrive, so D/A converter “knows” when to load the data into its registers. The third line is the DATA itself, for both channels, time multiplexed, so it firstly carries left channel, and then right channel binary word.

     

     

    Now, eight channel I2S has four of these DATA lines, each carrying two channels. In that way, this multichannel interface has the following outputs: MCK, WS (LRCK), BCK, and four DATA signals. If you use one 8 channel D/A converter chip, you just send all these signals to that chip. If you on the other hand use stereo D/A chip, or more single, dual or quad channel D/A chips for multichannel playback, you send WS (LRCK) and BCK signals to each of them (and MCK if it is required), plus necessary DATA signal(s).

     

     

    This leads us to the following block diagram for eight channel USB interface board.

     

     

     

    Philips TDA1541(A) simultaneous data protocol requires separate DATA line for each channel, and hence with this output protocol the number of channels will be limited to four.

     

    * – In practice, different manufacturers may use different names for these lines. Thus, BCK might be denoted as SCK (serial clock), and DATA as SD (serial data).

  2. 06-01-2018

    Apparently the interest in this multichannel USB interface is not actually very high, and consequently this idea might be abandoned. The form however remains open for some time still.

    On the other side, we will probably proceed with the idea of revised AYA II.

    I will post the final plans in one week or so.

  3. 26-01-2018

    I would like to thank to those who applied, but now it is official, we will abandon releasing the third series of USB interface, at least for the time being.

    As for the AYA II, the decision is to proceed with this new version. Generally, it will mate the AYA II you already know, with asynchronous USB interface, in its latest shape. ETA is Q2 2018. Official announcement, with other details, will follow.